In general, as the capacity of a semiconductor memory increases, the chip size becomes enlarged and the memory cell pattern has a higher density. In such situations, malfunctions are more likely to arise because of faulty bits, and the resulting yield is reduced. To overcome this problem, the common practice is to provide an extra row or column of memory cells in the semiconductor memory chip beforehand, and enable the extra row or column to take over for the row or column including a faulty bit. In this case, it is previously programmed so that a laser blowing occurs in the fuse so as to break the circuit in response to the occurrence of a fault on a bit.
Under the conventional practice mentioned above, it is necessary to ensure that when a regular memory cell column or row train is found to include a faulty bit, the regular memory cell train is electrically separated from the regular decoder, and then, the node thereof separated from the regular decoder which has been a terminal for an input signal to be applied to is fixed at the low logic level (hereinafter referred to as the "L" level). This means that the faulty regular memory cell train is kept at an unselected state, wherein the "faulty regular memory cell train" means a regular memory cell train including a faulty bit. This terminology will ensue in the following description.
For better understanding, reference will be more particularly made to FIG. 1, which shows a structural view of a known taking-over system:
The illustrated example is concerned with a regular selecting means for selecting a regular memory cell column train in a static RAM (random access memory). There are provided a decoder 1 for decoding an input address signal, the output 2 of which is connected to gates 11, 12 of MOS (metal oxide semiconductor) transistors 9, 10 through a fuse 3 of polisilicon, which is programmed to be melted or blown by a laser or similar means. The MOS transistors 9 and 10 for selecting a desired column are located in the regular memory cell column train 31 including regular memory cells in each column. There is provided an element of high resistance 4 connected between the gates 11, 12 and the ground, which element is made of polysilicon. The drains or sources of the MOS transistors 9, 10 are connected to bit lines 7, 8, respectively, and their sources (or drains) are connected to I/O (input/output) lines 5 and 6, respectively.
The system is operated as follows:
So long as the regular memory cell column train 31 is safe from a faulty bit, the fuse 3 allows a current to flow in a regular manner, thereby maintaining that the output 2 of the decoder 1 is connected to the gates 11, 12 of MOS transistors 9, 10, respectively. When the decoder output 2 is stepped up to a high logic level (hereinafter referred to as the "H" level), the MOS transistors 9, 10 turn on, thereby connecting the bit lines 7, 8 to the I/O lines 5, 6. In this way the stored information is read out.
On the other hand when the regular memory cell column train 31 includes a faulty bit, the fuse 3 is melted by a laser in accordance with the programmed instruction, thereby electrically disconnecting the decoder output 2 from the gates 11, 12 of the MOS transistors 9, 10. The electric charges at the gates 11, 12 are discharged to the ground through the element of high resistance 4, and the potentials of the gates 11, 12 are changed to the ground potential. In this way the MOS transistors 9, 10 are cut off, and the bit lines 7, 8 are electrically disconnected from the I/O lines 5, 6. As a result, the regular memory cell column train 31 illustrated in FIG. 1 is made ineffective on the read/write operation of the memory.
Meanwhile, in the extra memory cell group an extra selecting means starts to work so as to enable an extra memory cell column train to take over the faulty regular memory cell column train in accordance with the programmed instruction. That is, in the situation that the faulty regular memory cell column train 31 are disconnected from the I/O line, the extra selecting means for selecting an extra memory cell column train starts to work upon receipt of an address input signal which would otherwise be applied to the regular selecting means for selecting regular memory cell column train, thereby enabling the extra memory cell column train to take over the faulty regular memory cell column train.
As evident from the foregoing description, it is essential under the conventional practice to provide an element of high resistance 4 so as to keep the column train including a faulty memory cell in an unseleced state. In general, an element of high resistance is made of polysilicon or any other material of high resistance. In a full CMOS memory, in which a P-channel MOS transistor is employed for a load transistor, it is particularly necessary to fabricate such a resistance of polysilicon, a process which involves an extremely complicated processing steps. This results in the increased production cost.